1. Field of the Invention
The present invention relates to a semiconductor device having a circuit constituted by thin-film transistors (hereinafter abbreviated as TFTs) formed on a substrate having an insulating surface and to a method of fabricating the same. More particularly, the invention relates to an electro-optical device as represented by a liquid crystal display device having a pixel portion and a driver circuit formed in the periphery thereof on the same substrate, and technique that can be favorably utilized to electronic equipment mounting the electro-optical device. In this specification, the semiconductor device stands for devices that work by utilizing the semiconductor characteristics, in general, and encompasses the above-mentioned electro-optical device and electronic equipment mounting the electro-optical device.
2. Description of the Related Art
Technique for constituting switching elements and active circuits by using TFTs has been developed in connection with the electro-optical devices as represented by an active matrix-type liquid crystal display device. TFT is the one in which a semiconductor film is formed on a substrate such as of a glass by a vapor-phase growing method and is used as an active layer. As the semiconductor film, there is preferably used silicon or a material comprising chiefly silicon such as silicon-germanium. The semiconductor films can be classified into amorphous silicon films and crystalline silicon films as represented by polycrystalline silicon depending upon the method of formation.
The TFT using the amorphous semiconductor (typically, amorphous silicon) film is not capable of exhibiting an electric field effect mobility of not smaller than several square centimeters per Vsec due to electro-physical properties caused by the amorphous structure. In the liquid crystal display device of the active matrix type, therefore, the switching elements (pixel TFTs) can be formed for driving the liquid crystals in the pixel portion, but the driver circuit cannot be formed for displaying the picture. Therefore, the driver circuit is employing a technique for mounting a driver IC relying upon a TAB (tape automated bonding) system or a COG (chip on glass) system.
On the other hand, the TFT using, as an active layer, a semiconductor film including a crystal structure (hereinafter referred to as crystalline semiconductor) (typically, crystalline silicone or polycrystalline silicone), exhibits a high electric field effect mobility and makes it possible to form circuits of various functions on the same glass substrate and, hence, makes it possible to realize, in addition to pixel TFTs, a shift register circuit in a driver circuit, a level shifter circuit, a buffer circuit and a sampling circuit. Such circuits have been formed relying upon a CMOS circuit constituted by n-channel TFTs and p-channel TFTs. Owing to the above technique for mounting the driver circuits, it is becoming obvious that the TFTs having a crystalline semiconductor layer as an active layer is suited for forming the driver circuits in addition to the pixel portion on the same substrate, from the standpoint of decreasing the weight and thickness of the liquid crystal display device.
From the standpoint of TFT characteristics, it is better to use the crystalline semiconductor layer as an active layer. From the standpoint of fabricating the TFTs suited for various circuits in addition to the pixel TFTs, however, the steps of fabrication become complex and, besides, the number of the steps increase. It is obvious that an increase in the number of the steps drives up the cost of production and, besides, decreases the yield of production.
Further, in order to stabilize the operation of these circuits fabricated by using n-channel TFTs and p-channel TFTs, the threshold voltages and sub-threshold constants (S-values) of the TFTs must be confined within a predetermined range. For this purpose, the TFTs must be studied from both the structure and the materials constituting them.
The present invention deals with a technique for solving the above problems, and provides an electro-optical device as represented by a liquid crystal display device of the active matrix type fabricated by using the TFTs and a semiconductor device, wherein the TFTs arranged in the circuits have suitable structures depending upon the circuit functions, in order to improve operation characteristics and reliability of the semiconductor device, to decrease the consumption of electric power, to decrease the number of the steps, to decrease the cost of production and to improve the yield.
In order to decrease the cost of production and to improve the yield, the number of the steps may be decreased as one of the means. Concretely speaking, it is necessary to decrease the number of the photomasks required for the production of the TFTs. In the photolithographic technique, the photomask is used for forming, on the substrate, a resist pattern that serves as a mask in the etching step. Therefore, when the photomask is used, it means that there must be executed the steps of forming a film and etching before and after the step of using the photomask, as well as the steps of peeling the resist, washing and drying, as well as complex steps of applying the resist, prebaking, exposure to light, developing and post-baking even during the photolithography.
While decreasing the number of the photomasks, the TFTs arranged in various circuits have suitable structures depending upon the functions of the circuits. Concretely speaking, it is desired that the TFTs for the switching elements have a structure placing more importance on decreasing the off current than on the operation speed. For this structure, a multi-gate structure is employed. On the other hand, the TFTs used in the driver circuit that requires a high-speed operation should have a structure that places importance on the operation speed and on suppressing the deterioration caused by the injection of hot carriers, which is a serious problem. To accomplish this structure, contrivance is made to the LDD region of the TFT. That is, in the LDD region provided between the channel-forming region and the drain region, gradient is imparted to the concentration such that the concentration of impurity element for controlling the conduction type gradually increases toward the drain region. This constitution is effective in relaxing the concentration of the electric field in the depletion layer near the drain region.
In order to form the LDD region having such a gradient in the concentration of the impurity element according to this invention, the ionized impurity element for controlling the conduction type is accelerated through an electric field and is passed through the gate-insulating film (in this invention, both the gate-insulating film provided between the gate electrode and the semiconductor layer being intimately contacted thereto, and an insulating film extending in the peripheral region thereof from the gate-insulating film, are referred to as gate-insulating film) so as to be added to the semiconductor layer. In this specification, the method of adding the impurity element is called xe2x80x9cthrough doping methodxe2x80x9d from the standpoint of convenience. In the through doping method of the invention, the gate electrode has a so-called tapered shape in which the thickness of the gate electrode gradually increases toward the inside from an end portion thereof. The gate-insulating film, too, has a tapered shape in which the thickness gradually increases toward a portion that comes in contact with the gate electrode. Upon conducting the through doping method, therefore, the concentration of the impurity element added to the semiconductor layer is controlled by the thickness of the tapered gate insulating film, making it possible to form an LDD region in which the concentration of the impurity element gradually changes in the direction of channel length of the TFT.
The gate electrode is formed by using a heat-resistant electrically conductive material such as tungsten (W), tantalum (Ta) or titanium (Ti), or a compound of the above element, or an alloy thereof. The heat-resistant electrically conductive material is etched at a high speed and precisely forming an end in a tapered shape, relying upon a dry-etching method using a high-density plasma. A high-density plasma can be obtained by using an etching device utilizing microwaves or inductively coupled plasma (ICP). In particular, the ICP etching device easily controls the plasma and makes it possible to treat even those substrates having large areas.
The plasma processing method using ICP and the plasma processing apparatus have been disclosed in Japanese Patent Laid-Open No. 9-293600. According to this publication, the plasma processing is executed highly precisely by forming a plasma by applying a high-frequency electric power to a multi-spiral coil in which four spiral coils are connected in parallel via an impedance matching unit. Here, each coil has a length equal to one-fourth the wavelength of a high frequency. Further, the lower electrode for holding the work, too, is applied with a bias voltage by separately applying a high-frequency electric power thereto.
FIG. 17A schematically illustrates the plasma processing apparatus (e.g., etching device) using the ICP. An antenna coil 903 is arranged on a quartz plate 905 provided in an upper part of reaction space, and is connected to a first high-frequency power source 901 through a matching box 907. The first high-frequency power source 901 has a frequency of 6 to 60 MHz and, typically, 13.56 MHz. A lower electrode 904 for holding a substrate 906 which is a work to be treated, is connected to a second high-frequency power source 902 through a matching box 912. The second high-frequency power source 902 has a frequency of 100 kHz to 60 MHz (e.g., 6 to 29 MHz). When a high-frequency electric power is applied to the antenna coil 903, a high-frequency current J flows into the antenna coil 903 in a direction xcex8, and a magnetic field B generates in the direction Z,
xcexc0J=rotBxe2x80x83xe2x80x83(1)
According to Faraday""s electromagnetic induction rule, an induced electric field E generates in the direction xcex8,
xe2x88x92∂B/∂t=rot Exe2x80x83xe2x80x83(2)
In the induced electric field E, the electrons are accelerated in the direction xcex8 and come into collision with gas molecules to form a plasma. Since the electric field is induced in the direction xcex8, the probability is low in that the charged particles come into collision with the wall of the reaction chamber and the substrate to lose energy. The magnetic field B does not almost extend to the lower side of the antenna coil 903 and, hence, a high-density plasma region is formed extending like a flat plate. Upon adjusting the high-frequency electric power applied to the lower electrode 904, the plasma density and the bias voltages applied to the substrate 906 can be controlled independently of each other. It is further allowed to change the frequency of the high-frequency electric power depending upon the material of the work to be treated.
To obtain the inductively coupled plasma of a high density, the high-frequency current J must be supplied into the antenna coil with a low loss and, hence, the inductance must be decreased. This can be effectively done by splitting the antenna coil. FIG. 17B is a diagram illustrating the constitution thereof, wherein four spiral coils (multi-spiral coils) 910 are arranged on a quartz plate 911 and are connected to a first high-frequency power source 908 through a matching box 909. Here, if the length of each coil is set to be an integer times of one-fourth of the wavelength of the high frequency, a standing wave is formed on the coil enhancing a peak voltage that is generated.
The etching device using the ICP upon employing the multi-spiral coils makes it possible to favorably etch the heat-resistant electrically conductive material. The invention employs a dry etching device (Model E645-ICP) that uses ICP, manufactured by Matsushita Electric Industrial Co. FIG. 18 illustrates the results of examining the tapered shape at the end of the pattern of the tungsten film formed in a predetermined shape on a glass substrate. Here, the angle of the tapered portion is defined to be the one subtended by the surface of the substrate (horizontal plane) and the inclined portion of the tapered portion (angle denoted by xcex81 in FIG. 5). Here, the common conditions comprise a discharge electric power (high-frequency electric power, 13.56 MHz applied to the coil) of 3.2 W/cm2 and the use of an etching gas of CF4 and Cl2 maintaining a pressure of 1.0 Pa. FIG. 18A illustrates the dependency of bias power (13.56 MHz) applied to the substrate upon the angle xcex81 of the tapered portion. The flowing rate of the etching gas is 30 SCCM for both CF4 and Cl2. It is obvious that the angle xcex81 of the tapered portion can be varied over 70xc2x0 to 20xc2x0 with the bias power in a range of from 128 to 384 mW/cm2. FIG. 18B illustrates the results of examining the dependency of the angle xcex81 of the tapered portion upon the flow rate of the etching gas. The flow rate of the sum of CF4 and Cl2 was set to be 60 SCCM, and CF4 only was varied over a range of 20 to 40 SCCM. The bias power at this moment was 128 mW/cm2. As a result, the angle xcex81 of the tapered portion could be varied over 60xc2x0 to 80xc2x0.
As described above, the angle of the tapered portion varies greatly depending upon the bias power applied to the substrate. The angle of the tapered portion can be varied over 5xc2x0 to 45xc2x0 by further increasing the bias power and changing the pressure.
In this invention, the gate-insulating film in contact with the end of the gate electrode, too, is tapered. FIG. 5 is a view illustrating a portion of an n-channel TFT on an enlarged scale. Here, the angle of the tapered portion of the gate-insulating film is defined to be the one subtended by the surface of the substrate (horizontal plane) and the inclined portion of the tapered portion (angle xcex82 in FIG. 5). The LDD region 623 is formed under the tapered portion 627 of the gate-insulating film. The distribution of concentration of phosphorus (P) in the LDD region is represented by a curve 625, and increases as it goes away from the channel-forming region 621.
The rate of increase varies depending upon the conditions such as acceleration voltage at the time of ion doping and dosage thereof, angles xcex82 and xcex81 of the tapered portions 627 and 628, and the thickness of the gate electrode 607. Thus, the end of the gate electrode and the gate-insulating film in the vicinity thereof are tapered, and impurity elements are added through the tapered portion in order to form an impurity region in which the concentration of the impurity element gradually changes in the semiconductor layer under the tapered portion. Further, the end 622 of the LDD region is overlapped on the gate electrode 607. Depending upon the doping conditions, however, the gate electrode and the LDD may be so arranged as will not be overlapped one upon the other.
Depending upon the etching conditions, further, the gate-insulating film may assume a shape as shown in FIG. 16A. An LDD region 1623 is formed under the tapered portion of the gate-insulating film shown in FIG. 16A. In FIG. 16A, reference numeral 1605 denotes a gate-insulating film, 1607 denotes a gate electrode, 1621 denotes a channel-forming region, 1622 denotes an LDD region superposed on the gate electrode, and 1624 denotes a source region or a drain region.
Depending upon the etching conditions, further, the gate-insulating film may assume a shape as shown in FIG. 16B. An LDD region 1723 is formed under the tapered portion of the gate-insulating film shown in FIG. 16A. In FIG. 16B, reference numeral 1705 denotes a gate-insulating film, 1707 denotes a gate electrode, 1721 denotes a channel-forming region, 1722 denotes an LDD region overlapped on the gate electrode, and 1724 denotes a source region or a drain region. In FIG. 16B, further, a step is formed in the tapered portion, and the region of a length L3 from the end of the gate electrode has the gate-insulating film of a thickness equal to the film thickness under the gate electrode.
Table 1 shows working characteristics of the heat-resistant electrically conductive material of before the gate electrode is formed by using the ICP etching apparatus. Shown here is an example of a molybdenum-tungsten (Moxe2x80x94W) alloy (composition ratio of Mo:W=48:50% by weight) that is frequently used as a material of gate electrode in addition to the W film and the Ta film. Table 1 shows representative values related to the etching rate, etching gas that is used, and a selection ratio to the gate-insulating film that serves as an underlayer of the gate electrode. The gate-insulating film is a silicon oxide film or a silicon oxynitride film formed by the plasma CVD method. Here, the selection ratio is defined to be a ratio of the etching rate of the material to the etching rate of the gate-insulating film.
The rate of etching the Ta film is 140 nm/min to 160 nm/min, the selection ratio thereof is 6 to 8, the rate of etching the W film is 70 nm/min to 90 nm/min, and the selection ratio thereof is 2 to 4, which are excellent values. From the standpoint of workability, therefore, the Ta film is suited. However, though not shown in Table 1, the Ta film has a resistivity of from 20 xcexcxcexa9cm to 30 xcexcxcexa9cm which is larger than 10 xcexcxcexa9cm to 16 xcexcxcexa9cm of the W film. On the other hand, Moxe2x80x94W alloy exhibits an etching ratio of as slow as 40 nm/min to 60 nm/min and its selection ratio is from 0.1 to 2. Therefore, this material is not necessarily suited from the standpoint of workability. It is thus learned from Table 1 that the Ta film gives the best results. By taking the resistivity into consideration, however, it is considered that the W film is suited from an overall point of view.
Though the W film was described above as the heat-resistant electrically conductive material, the end of its pattern can be easily tapered by using the ICP etching apparatus. Then, the gate electrode is formed by the above method, and the through doping method is executed to control the concentration of the impurity element added to the semiconductor layer relying upon the thickness of the gate-insulating film. It is thus allowed to form the LDD region in which the concentration of the impurity element gradually changes in the lengthwise direction of the channel of the TFT.
By using the above means, the constitution of this invention is concerned with a semiconductor device comprising an active layer of a thin semiconductor film formed on a substrate having an insulating surface, an insulating film covering the active layer, and a gate electrode formed on the insulating film, wherein:
the active layer has a channel-forming region superposed on the gate electrode, a region of a low impurity concentration for forming the LDD region, and a source region or a drain region; and
the insulating film on the region of a low impurity concentration has a thickness smaller than the thickness thereof on the channel-forming region but is larger than the thickness thereof on the source region or the drain region.
In the above constitution, the gate electrode has a tapered portion.
In the above constitution, further, the region of a low impurity concentration exists between the channel-forming region and the source region or between the channel-forming region and the drain region.
In the above constitution, further, the concentration of the p-type or n-type impurity element contained in the region of the low impurity concentration increases as it goes away from the channel-forming region.
In the above constitution, further, the source region or the drain region contains a p-type or an n-type impurity element at a concentration higher than the concentration of the p-type or n-type impurity element contained in the region of the low impurity concentration.
In the above constitution, further, the concentration of the p-type or n-type impurity element contained in the region of the low impurity concentration is from 1xc3x971016 atoms/cm3 to 1xc3x971020 atoms/cm3.
In the above constitution, further, the insulating film covering the active layer has a tapered portion, the length L2 of the tapered portion being from 0.1 xcexcm to 1 xcexcm in the lengthwise direction of the channel.
In the above constitution, further, the gate electrode is a single-layer film or a laminated-layer film of a heat-resistant electrically conductive material, and the heat-resistant electrically conductive material is an element selected from tantalum (Ta), titanium (Ti) and tungsten (W), or is a compound of the above element, or a compound of a combination of the above elements, or a nitride of the above element, or a silicide of the above element.
In the above constitution, further, the gate electrode is tapered at an angle of 5xc2x0 to 35xc2x0.
To obtain the above constitution, further, the invention deals with a method of fabricating a semiconductor device having, formed on the same substrate, pixel TFTs provided in a pixel portion and a driver circuit including p-channel TFTs and n-channel TFTs in the peripheries of the pixel portion, comprising:
a first step of forming a semiconductor layer containing a crystalline structure on the substrate;
a second step of forming plural island-like semiconductor layers by selectively etching the semiconductor layer that contains the crystalline structure;
a third step of forming a gate-insulating film in contact with the island-like semiconductor layers;
a fourth step of forming an electrically conductive layer of a heat-resistant electrically conductive material on the gate-insulating film;
a fifth step of forming a gate electrode having a tapered portion and a gate-insulating film having a tapered portion by selectively etching the electrically conductive layer;
a sixth step of forming a region of a low n-type impurity concentration in the island-like semiconductor layers that form the n-channel TFTs of the driver circuit and the pixel TFTs by adding an n-type impurity element through the tapered portion of the gate-insulating film, the region of the low n-type impurity concentration having a gradient of concentration of the n-type impurity element in a direction in parallel with the substrate;
a seventh step of forming a region of a high n-type impurity concentration in the island-like semiconductor layers that form the n-channel TFTs of the driver circuit and the pixel TFTs by adding an n-type impurity element using the gate electrode as a mask:
an eighth step of forming a region of a low p-type impurity concentration in the island-like semiconductor layer that forms the p-channel TFTs of the driver circuit by adding a p-type impurity element through the tapered portion of the gate electrode and the gate-insulating film, the region of the low p-type impurity concentration having a gradient of concentration of the p-type impurity element in a direction in parallel with the substrate, and, at the same time, forming a region of a high p-type impurity concentration therein by adding a p-type impurity element without through the tapered portion of the gate electrode;
a ninth step of forming a first interlayer-insulating film of an inorganic insulating material on the n-channel TFTs of the driver circuit, on the pixel TFTs and on the p-channel TFTs;
a tenth step of forming a second interlayer-insulating film or an organic insulating material in contact with the first interlayer-insulating film; and
an eleventh step of forming pixel electrodes connected to said pixel TFTs on said second interlayer-insulating film.
In the above-constitution, further, the fifth step of forming the gate electrode having the tapered portion and of forming the gate-insulating film having the tapered portion by selectively etching the electrically conductive layer, may be the one that is executed through one time of etching or may be the one that is executed through plural times of etching.